VHDL hardware synthesis, Novel Microprocessor Architectures, Stack-based processors, Optimisation of Stack-oriented object code, Multimedia Server Architectures and Bus arbitration methods.
1996-1997 - Teaching Research Fellow.
1997-1999 - Senior Lecturer University of Teeside.
1999-Present - Lecturer, University of York
Phone: +44 (0)1904 325659
Office: CSE/134E-mail: Send e-mail using web form
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