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Circuit Bipartitioning Using Genetic Algorithm
Jong-Pil Kim and Byung-Ro Moon
School of Computer Science and Engineering
Seoul National University
Shilim-dong, Kwanak-gu
Seoul, 151-742 Korea
{jpkim,moon}@soar.snu.ac.kr
Abstract. In this paper, we propose a hybrid genetic algorithm for partitioning a VLSI circuit graph into two disjoint graphs of minimum cut size. The algorithm includes a local optimization heuristic which is a modification of Fiduccia-Matheses algorithm. Using well-known benchmarks (including ACM/SIGDA benchmarks), the combination of genetic algorithm and the local heuristic outperformed hMetis [3], a representative circuit partitioning algorithm.
LNCS 2724, p. 2408 ff.
lncs@springer.de
© Springer-Verlag Berlin Heidelberg 2003