This is a project to investigate the strategies for power consumption reduction in communication networks implemented upon a silicon chip, such as in modern multicore CPUs and system-on-chip (SoC) devices. Networks-On-Chip (NoCs) replace the bottleneck of custom point-to-point wires routed on the silicon die with a standardised communications network, bringing the same benefits of abstraction and layering seen in standard communication networks to SoCs.

The essential goal which this project addresses is the reduction of the dynamic power consumption of NoCs. Early research has shown that up a third of the total power consumed in these systems is consumed by the NoC. Therefore, techniques to reduce power consumption are of tremendous value as NoCs scale up to larger and larger sizes in realistic applications.

The project is taking place in the Real-Time Systems Group of the Computer Science Department of the University of York, and the principal investigator is Dr Leandro Soares Indrusiak. Dr James Harbin is the Research Associate working on the project.

The goals of the project are as follows:

1. Extend the lsi.noc simulation framework (developed in Java upon the Ptolemy II simulator) to incorporate NoC power modelling
2. Investigate dynamic task mapping heuristics, which move processing tasks around the multicore system to reduce NoC power dissipation
3. Investigate link coding algorithms (in particular adaptive link coding) in order to reduce dynamic power consumption upon NoC links and routers