This paper presents an approach supporting designerdriven interactive design space exploration for Networkon- Chip interconnects. It abstracts the functionality of the interconnect using UML interactions, which are in turn used as reference for the development of an actor-oriented model. Such model can be annotated with timing information, thus allowing the validation of the interconnect performance under a given traffic load. The proposed model allows simpler tuning and modification of the interconnect, improved observability and debugging, while presenting acceptable loss of accuracy with regard to a cycle-accurate RTL model.
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BibTex Entry

@inproceedings{Indrusiak2008,
 author = {L. S. Indrusiak and L. Ost and L. Moller and F. Moraes and M. Glesner},
 booktitle = {Proc. IEEE Computer Society Annual Symposium on VLSI (ISVLSI)},
 pages = {491-494},
 publisher = {IEEE Computer Society},
 title = {Applying UML Interactions and Actor-oriented Simulation to the Design Space Exploration of Network-on-Chip Interconnects},
 year = {2008}
}