Hardware Implementation of the Ravenscar Tasking Profile

Real-Time Systems place large demands on the languages used to implement them. Processor based implementation methods do not allow accurate timing analysis of systems due to the complexity of modern processors. FPGAs provide a means to implement a real-time system in a way that allows accurate timing analysis to be performed. Existing hardware implementations of high-level programming languages do not support the needs of real-time systems. This paper presents a hardware implementation of the SPARK Ravenscar subsets of Ada which can be accurately analysed for its timing properties. A method of compiling sequential Ada programs has been described elsewhere, and this is expanded to include the compilation of protected objects and tasks. The effect this has on the ability to analyse the timing of the program is then examined.