A Self-Optimising Simulator For a Coarse-Grained Reconfigurable Array
Jack Whitham and Neil Audsley
This paper describes the implementation and testing of a high-speed simulator for a reconfigurable processor architecture named MCGREP. The architecture is based on a coarse-grained array of small processors controlled by reconfigurable microcode. A high-speed simulator is needed to allow complex experiments to be carried out on MCGREP, involving large applications and time-consuming computations. Contributions include descriptions of methods for generating, using and testing a simulator for a coarse-grained reconfigurable architecture (CGRA). Special issues that are handled include a requirement to convert MCGREP microcode into native code at any time during execution, and a need to support architectural extensions for future experiments.
BibTex Entry
@proceedings{Whitham2007,
author = {Jack Whitham and Neil Audsley},
editor = {Albert Koelmans},
month = {April},
publisher = {University of Newcastle},
series = {UK Embedded Forum},
title = {A Self-Optimising Simulator For a Coarse-Grained Reconfigurable Array},
volume = {3},
year = {2007}
}