Prefetching Across a Shared Memory Tree within a Network-on-Chip Architecture
Jamie Garside and Neil C Audsley
Within Network-on-Chip architectures the sharing of external memory by many CPUs provides a key challenge within the design in order that memory latencies do not dominate overall performance. Within this paper, we propose and evaluate a stream based prefetch unit within a NoC architecture that utilises a separate shared memory tree to provide access to external memory from each CPU tile. The paper shows that prefetching is an appropriate architectural technique within NoCs, enabling better system performance.
BibTex Entry
@inproceedings{Garside2013a,
address = {Tampere},
author = {Jamie Garside and Neil C Audsley},
booktitle = {International Symposium on System-on-Chip 2013},
file = {:Users/jamie/Documents/Papers/jg-uoy-soc2013.press.pdf:pdf},
title = {Prefetching Across a Shared Memory Tree within a Network-on-Chip Architecture},
volume = {1},
year = {2013}
}