Exploring Heterogeneous NoC-based MPSoCs: from FPGA to High-Level Modeling
L. Ost, G. M. Almeida, M. Mandelli, E. Wachter, S. Varyani, L. S. Indrusiak, G. Sassatelli, M. Robert and F. Moraes
This paper proposes a novel strategy for enabling dynamic task mapping on heterogeneous NoC-based MPSoC architectures. The solution considers three different platforms with different area constraints and applications with distinct efficient characteristics. We propose a solution that uses a unified model-based framework, which is calibrated according to area information obtained from FPGA synthesis. Besides, we present the performance of various applications running on different processors on FPGAs aiming to obtain application efficiency characteristics for calibrating the proposed high-level model. The paper also presents three different scenarios and discusses the reduction in terms of energy consumption as well as the end-to end communication cost for different applications such as MPEG and ADPCM, among others multimedia benchmarks.
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BibTex Entry
@inproceedings{Ost2011a,
author = {L. Ost and G. M. Almeida and M. Mandelli and E. Wachter and S. Varyani and L. S. Indrusiak and G. Sassatelli and M. Robert and F. Moraes},
booktitle = {Proc of the 6th Int Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)},
title = {Exploring Heterogeneous NoC-based MPSoCs: from FPGA to High-Level Modeling},
year = {2011}
}