CASES 2006 Table of Contents

Message from the General Co-Chairs
Seongsoo Hong and Wayne Wolf (CASES’06 General Co-Chairs)

Message from the Program Co-Chairs
Krisztian Flautner and Taewhan Kim (CASES'06 Program Co-Chairs)

CASES 2006 Conference Organization, Committees, Reviewers

Keynote Address

Dances with Multimedia — Embedded Video Codec Design (Page 1)
L.-G. Chen (National Taiwan University)

Session 1: Modeling and Simulation

An Accurate and Efficient Simulation-Based Analysis for Worst Case Interruption Delay (Page 2)
H. Nakashima, M. Konishi, T. Nakada (Toyohashi University of Technology)

Reaching Fast Code Faster: Using Modeling for Efficient Software Thread Integration on a VLIW DSP (Page 13)
W. So, A. G. Dean (North Carolina State University)

Automatic Performance Model Construction for the Fast Software Exploration of New Hardware Designs (Page 24)
J. Cavazos, C. Dubach, F. Agako, E. Bonilla, M. F. P. O'Boyle (University of Edinburgh)
G. Fursin, O. Temam (Paris-Sud University)

Session 2: Short Presentations with Posters I

Supporting Precise Garbage Collection in Java Bytecode-to-C Ahead-of-Time Compiler for Embedded Systems (Page 35)
D.-H. Jung, S.-H. Bae, J. Lee, S.-M. Moon , JK. Park (Seoul National University)

Adapting Compilation Techniques to Enhance the Packing of Instructions into Registers (Page 43)
S. Hines, D. Whalley, G. Tyson (Florida State University)

Modeling Heterogeneous SoCs with SystemC: A Digital/MEMS Case Study (Page 54)
A. Varma (University of Maryland & National Institute of Standards and Technology)
M. Y. Afridi (National Institute of Standards and Technology)
A. Akturk (University of Maryland)
P. Klein (Intel Corporation)
A. R. Hefner (National Institute of Standards and Technology)
B. Jacob (University of Maryland)

A Network Agent for Diagnosis and Analysis of Real-time Ethernet Networks (Page 65)
H.-P. Löb (Infineon Technologies AG)
R. Buchty, W. Karl (Universität Karlsruhe)

Memory Optimization by Counting Points in Integer Transformations of Parametric Polytopes (Page 74)
R. Seghir, V. Loechner (Université Louis Pasteur)

State Space Reconfigurability: An Implementation Architecture for Self Modifying Finite Automata (Page 83)
K.-M. Keung, A. Tyagi (Iowa State University)

Incremental Elaboration for Run-Time Reconfigurable Hardware Designs (Page 93)
A. Derbyshire, T. Becker, W. Luk (Imperial College London)

FlashCache: A NAND Flash Memory File Cache for Low Power Web Servers (Page 103)
T. Kgil , T. Mudge (The University of Michigan)

Session 3: Compilation 

Adaptive and Flexible Dictionary Code Compression for Embedded Applications (Page 113)
M. Brorsson, M. Collin (KTH ICT)

Automated Compile-Time and Run-Time Techniques to Increase Usable Memory in MMU-Less Embedded Systems (Page 125)
L. S. Bai, L. Yang, R. P. Dick (Northwestern University)

Modulo Graph Embedding: Mapping Applications onto Coarse-Grained Reconfigurable Architectures (Page 136)
H. Park, K. Fan, M. Kudlur, S. Mahlke (University of Michigan)

Scalable Subgraph Mapping for Acyclic Computation Accelerators (Page 147)
N. Clark, A. Hormati, S. Mahlke (University of Michigan)
S. Yehia (ARM Ltd.)

Session 4: Architecture / Power

Probabilistic Arithmetic and Energy Efficient Embedded Signal Processing (Page 158)
J. George , B. Marr, B. E. S. Akgul, K. V. Palem (Georgia Institute of Technology)

Power Efficient Branch Prediction through Early Identification of Branch Addresses (Page 169)
C. Yang, A. Orailoglu (University of California at San Diego)

Reducing Energy of Virtual Cache Synonym Lookup using Bloom Filters (Page 179)
D. H. Woo (Georgia Institute of Technology)
M. Ghosh (Georgia Institute of Technology)
E. Özer (ARM Ltd.)
S. Biles (ARM Ltd.)
H.-H. S. Lee (Georgia Institute of Technology)

Efficient Architectures through Application Clustering and Architectural Heterogeneity (Page 190)
L. Strozek, D. Brooks (Harvard University)

Session 5: Memory Systems

Minimizing Bank Selection Instructions for Partitioned Memory Architectures (Page 201)
B. Scholz (The University of Sydney)
B. Burgstaller (The University of Sydney)
J. Xue (University of NSW)

Protected Heap Sharing for Memory-Constrained Java Environments (Page 212)
Y. Choi, H. Han (Korea Advanced Institute of Science of Technology)

A Dynamic Code Placement Technique for Scratchpad Memory Using Postpass Optimization (Page 223)
B. Egger, C. Kim, C. Jang, Y. Nam, J. Lee, S. L. Min (Seoul National University)

CFLRU: A Replacement Algorithm for Flash Memory (Page 234)
S.-y. Park, D. Jung, J.-u. Kang, J.-s. Kim, J. Lee (Korea Advanced Institute of Science of Technology)

Session 6: Short Presentations with Posters II

Code Tranformation Strategies for Extensible Embedded Processors (Page 242)
P. Bonzini, L. Pozzi (University of Lugano)

Syntax-Driven Implementation of Software Programming Language Control Constructs and Expressions on FPGAs (Page 253)
N. C. Audsle, M. Ward (University of York)

A Dynamic Binary Instrumentation Engine for the ARM Architecture (Page 261)
K. Hazelwood (University of Virginia)
A. Klauser (Intel Corporation)

High-Level Languages for Small Devices: A Case Study (Page 271)
M. Carro (Universidad Politécnica de Madrid)
J. F. Morales (Universidad Complutense de Madrid)
H. L. Muller (University of Bristol)
G. Puebla (Universidad Politécnica de Madrid)
M. Hermenegildo (Universidad Politécnica de Madrid & University of New Mexico)

Adaptive Object Code Compression (Page 282)
J. Gilbert , D. M. Abrahamson (Trinity College Dublin)

Limitations of Special-Purpose Instructions for Similarity Measurements in Media SIMD Extensions (Page 293)
A. Shahbahrami, B. Juurlink, S. Vassiliadis (Delft University of Technology)

Entropy-Based Low Power Data TLB Design (Page 304)
C. Ballapuram, K. Puttaswamy, G. H. Loh, H.-H. S. Lee (Georgia Institute of Technology)

Compiler Optimization of Embedded Applications for an Adaptive SoC Architecutre (Page 312)
C. R. Hardnett (Spelman College)
K. V. Palem (Georgia Institute of Technology)
Y. Chobe (Georgia Institute of Technology)

Session 7: Multithreading and Multiprocessing

Extensible Control Architectures (Page 323)
G. Hoover, F. Brewer, T. Sherwood (University of California at Santa Barbara)

High-performance Packet Classification Algorithm for Many-core and Multithreaded Network Processor (Page 334)
D. Liu, B. Hua, X. Hu (University of Science and Technology of China)
X. Tang (Intel Compiler Laboratory)

Improving the Performance and Power Efficiency of Shared Helpers in CMPs (Page 345)
A. Shayesteh, G. Reinman (University of California at Los Angeles)
N. Jouppi (Hewlett Packard Laboratories)
T. Sherwood (University of California at Santa Barbara)
S. Sair (North Carolina State University)

A Case Study of Multi-Threading in the Embedded Space (Page 357)
G. Hoover, F. Brewer, T. Sherwood (University of California at Santa Barbara)

Session 8: Low Power 

Architecture and Circuit Techniques for Low-Throughput, Energy-Constrained Systems Across Technology Generations (Page 368)
M. Hempstead, G.-Y. Wei, D. Brooks (Harvard University)

Methods for Power Optimization in Distributed Embedded Systems with Real-Time Requirements (Page 379)
R. Racu, A. Hamann, R. Ernst (Technical University of Braunschweig)
B. Mochocki (University of Notre Dame)
X. S. Hu (University of Notre Dame)

High-Level Power Analysis for Multi-Core Chips (Page 389)
N. Eisley, V. Soteriou, L.-S. Peh (Princeton University)

Session 9: Robustness

Integrated Scratchpad Memory Optimization and Task Scheduling for MPSoC Architectures (Page 401)
V. Suhendra, C. Raghavan, T. Mitra (National University of Singapore)

Mitigating Soft Error Failures for Multimedia Applications by Selective Data Protection (Page 411)
K. Lee, A. Shrivastava, I. Issenin, N. Dutt, N. Venkatasubramanian (University of California at Irvine)

Cost-Efficient Soft Error Protection for Embedded Microprocessors (Page 421)
J. A. Blome (University of Michigan)
S. Gupta (University of Michigan)
S. Feng (University of Michigan)
S. Mahlke (University of Michigan)
D. Bradley (ARM Ltd.)