CODES+ISSS'06 Table of Contents

Message from the Chairs
Reinaldo Bergamaschi (General Chair)
Soonhoi Ha and Kiyoung Choi (Technical Program Co-Chairs)

CODES+ISSS'06 Organizing Committee

CODES+ISSS'06 Technical Program Committee

CODES+ISSS'06 Steering Committee

Additional Reviewers

Tutorial 1 

UML and Model-Driven Development for SoC Design (Page 1)
W. Mueller (Paderborn University/C-LAB)
Y. Vanderperren (Katholieke Universiteit Leuven)

Tutorial 2 

Automotive Electronics: System, Software, and Local Area Network (Page 2)
Y. Furukawa (Shibaura Institute of Technology)
S. Kawamura (AutoNetworks Technologies)

Keynote 

Promises and Challenges of Mobile Embedded System: An Industry Perspective (Page 3)
N.-S. Woo (Samsung Electronics)

Session A1: HW/SW Design Exploration for Multimedia Applications 

Application-specific Workload Shaping in Multimedia-enabled Personal Mobile Devices (Page 4)
B. Raman, S. Chakraborty (National University of Singapore)

Efficient Computation of Buffer Capacities for Multi-Rate Real-Time Systems with Back-Pressure (Page 10)
M. Wiggers (University of Twente)
M. Bekooij (Philips Research)
P. Jansen, G. Smit (University of Twente)

Design Space Exploration of Real-time Multi-media MPSoCs with Heterogeneous Scheduling Policies (Page 16)
M. Kim, S. Banerjee, N. Dutt, N. Venkatasubramanian (University of California at Irvine)

Session A2: Low Power Scheduling and Estimation Techniques 

Battery Discharge Aware Energy Feasibility Analysis (Page 22)
H. Lipskoch, K. Albers, F. Slomka (University Oldenburg)

A Run-Time, Feedback-Based Energy Estimation Model for Embedded Devices (Page 28)
S. Gurun, C. Krintz (University of California at Santa Barbara)

Hardware Based Frequency/Voltage Control of Voltage Frequency Island Systems (Page 34)
P. Choudhary, D. Marculescu (Carnegie Mellon University)

Session A3: System-Level Performance Issues 

A Formal Approach to Robustness Maximization of Complex Heterogeneous Embedded Systems (Page 40)
A. Hamann, R. Racu, R. Ernst (Technical University of Braunschweig)

Automatic Run-Time Extraction of Communication Graphs from Multithreaded Applications (Page 46)
A.-H. Liu, R. P. Dick (Northwestern University)

The Pipeline Decomposition Tree: An Analysis Tool for Multiprocessor Implementation of Image Processing Applications (Page 52)
D.-I. Ko, S. S. Bhattacharyya (University of Maryland)

Session A4: Transaction-Level Modeling and Exploration 

TLM/Network Design Space Exploration for Networked Embedded Systems (Page 58)
N. Bombieri, F. Fummi, D. Quaglia (Università di Verona)

Automatic Generation of Transaction-Level Models for Rapid Design Space Exploration (Page 64)
D. Shin, A. Gerstlauer, J. Peng, R. Dömer, D. D. Gajski (University of California at Irvine)

Accurate Yet Fast Modeling of Real-Time Communication (Page 70)
G. Schirner, R. Dömer (University of California at Irvine)

Session A5: Architecture and Modeling for Network-on-Chip 

Bounded Arbitration Algorithm for QoS-Supported On-chip Communication (Page 76)
M. A. Al Faruque, G. Weiss, J. Henkel (University of Karlsruhe)

Increasing the Throughput of an Adaptive Router in Network-on-Chip (NoC) (Page 82)
S. E. Lee, N. Bagherzadeh (University of California at Irvine)

Automatic Phase Detection for Stochastic On-Chip Traffic Generation (Page 88)
A. Scherrer (LIP - ENS Lyon)
A. Fraboulet, T. Risset (CITI-INSA Lyon)

Session A6: Embedded Security and Reliability 

Methodology for Attack on a Java-based PDA (Page 94)
C. H. Gebotys, B. A. White (University of Waterloo)

Hardware Assisted Pre-emptive Control Flow Checking for Embedded Processors to Improve Reliability (Page 100)
R. G. Ragel, S. Parameswaran (University of New South Wales and National ICT Australia)

Architectural Support for Safe Software Execution on Embedded Processors (Page 106)
D. Arora (Princeton University)
A. Raghunathan, S. Ravi (NEC Laboratories America)
N. K. Jha (Princeton University)

Session A7: Advanced Techniques for High-Level Synthesis and Physical Design

Droplet-Trace-Based Array Partitioning and a Pin Assignment Algorithm for the Automated Design of Digital Microfluidic Biochips (Page 112)
T. Xu, K. Chakrabarty (Duke University)

Floorplan Driven Leakage Power Aware IP-Based SoC Design Space Exploration (Page 118)
A. Gupta, N. Dutt, F. Kurdahi (University of California at Irvine)
K. Khouri, M. Abadir (Freescale Semiconductor Inc.)

Thermal-Aware High-level Synthesis Based on Network Flow Method (Page 124)
P. Lim, T. Kim (Seoul National University)

Session A8: Design Optimization for Network-on-Chip

A Buffer-Sizing Algorithm for Networks on Chip Using TDMA and Credit-Based End-to-End Flow Control (Page 130)
M. Coenen (Philips Research)
S. Murali (Stanford University)
A. Rădulescu, K. Goossens (Philips Research)
G. De Micheli (LSI, EPFL)

Layout Aware Design of Mesh Based NoC Architectures (Page 136)
K. Srinivasan, K. S. Chatha (Arizona State University)

A Methodology for Design of Application Specific Deadlock-free Routing Algorithms for NoC Systems (Page 142)
M. Palesi (University of Catania)
R. Holsmark, S. Kumar (Jönköping University)

Session A9: Application-Specific Code Optimization 

Retargetable Code Optimization with SIMD Instructions (Page 148)
M. Hohenauer, C. Schumacher, R. Leupers, G. Ascheid, H. Meyr (RWTH Aachen University)
H. van Someren (Associated Compiler Experts bv)

Pack Instruction Generation for Media Processors Using Multi-valued Decision Diagram (Page 154)
T. Hiroaki, Y. Takeuchi, K. Sakanushi, M. Imai (Osaka University)
Y. Ota, N. Matsumoto, M. Nakagawa (Toshiba Corporation)

Automatic Selection of Application-Specific Instruction-Set Extensions (Page 160)
C. Galuzzi, E. M. Panainte, Y. Yankova, K. Bertels, S. Vassiliadis (Delft University of Technology)

Panel

Are Current ESL Tools Meeting the Requirements of Advanced Embedded Systems? (Page 166)
J. Teich (University of Erlangen-Nuremberg)

Special Session A10: Programming Models for Multiprocessor Systems: From Supercomputing Programming to Multiprocessors on a Chip 

Invited Paper: SHAPES: A Tiled Scalable Software Hardware Architecture Platform for Embedded Systems (Page 167)
P. S. Paolucci (Fisica Università Roma)
A. A. Jerraya (TIMA INPG)
R. Leupers (Aachen University of Technology)
L. Thiele (Swiss Federal Institute of Technology)
P. Vicini (Fisica Università Roma "La Sapienza")

Invited Paper: Challenges in Exploitation of Loop Parallelism in Embedded Applications (Page 173)
A. Kejariwal, A. V. Veidenbaum, A. Nicolau (University of California at Irvine)
M. Girkar, X. Tian, H. Saito (Intel Corporation)

Invited Paper: Resource Virtualization in Real-Time CORBA Middleware (Page 181)
C. D. Gill (Washington University)

Session A11: Simulation, Optimization, and Acceleration 

Phase Guided Sampling for Efficient Parallel Application Simulation (Page 187)
J. Namkung, D. Kim, R. Gupta (University of California at San Diego)
I. Kozintsev, J.-Y. Bouget, C. Dulong (Intel Corporation)

A Multiprocessing Approach to Accelerate Retargetable and Portable Dynamic-compiled Instruction-set Simulation (Page 193)
W. Qin (Boston University)
J. D'Errico (Cavium Networks, Inc.)
X. Zhu (Northeastern University)

B2Sim: A Fast Micro-Architecture Simulator Based on Basic Block Characterization (Page 199)
W. Lee, K. Patel, M. Pedram (University of Southern California)

Session A12: System-Level Design of MPSoC 

Decision-theoretic Exploration of Multi-Processor Platforms (Page 205)
G. Beltrame, D. Bruschi, D. Sciuto, C. Silvano (Politecnico di Milano)

Multi-processor System Design with ESPAM (Page 211)
H. Nikolov, T. Stefanov, E. Deprettere (Leiden University)

Heterogeneous Multiprocessor Implementations for JPEG: A Case Study (Page 217)
S. L. Shee (The University of New South Wales & National Information and Communications Technology Australia)
A. Erdos (The University of New South Wales)
S. Parameswaran (The University of New South Wales & National Information and Communications Technology Australia)

Session A13: System-Level Optimization 

Fuzzy Decision Making in Embedded System Design (Page 223)
A. G. Di Nuovo, M. Palesi, D. Patti (Università degli Studi di Catania)

Demand Paging for OneNANDTM Flash eXecute-In-Place (Page 229)
Y. Joo , Y. Choi (Seoul National University)
C. Park (Samsung Electronics)
S. W. Chung (Korea University)
E.-Y. Chung (Yonsei University)
N. Chang (Seoul National University)

Creation and Utilization of a Virtual Platform for Embedded Software Optimization: An Industrial Case Study (Page 235)
S. Hong, S. Yoo, Sheayun Lee, Sangwoo Lee, H. J. Nam, B.-S. Yoo, J. Hwang, D. Song, Janghwan Kim, Jeongeun Kim, HS. Jin, K.-M. Choi, J.-T. Kong, SK. Eo (Samsung Electronics Co., Ltd.)

Session A14: Architecture Exploration 

Application Specific Forwarding Network and Instruction Encoding for Multi-pipe ASIPs (Page 241)
S. Radhakrishnan, H. Guo, S. Parameswaran, A. Ignjatovic (University of New South Wales)

A Bus Architecture for Crosstalk Elimination in High Performance Processor Design (Page 247)
W.-W. Hsieh, P.-Y. Chen, T. T. Hwang (National Tsing Hua University)

Yield Prediction for Architecture Exploration in Nanometer Technology Nodes: A Model and Case Study for Memory Organizations (Page 253)
A. Papanikolaou, T. Grabner, M. Miranda, P. Roussel, F. Catthoor (IMEC vzw)

A Unified Hardware/Software Runtime Environment for FPGA-Based Reconfigurable Computers Using BORPH (Page 259)
H. K.-H. So, A. Tkachenko, R. Brodersen (University of California at Berkeley)

Special Session A15: Industry Solutions to Emerging Embedded Systems

Invited Talk: Cutting Across Layers of Abstraction: Removing Obstacles from the Advancement of Embedded Systems (Page 265)
K. Flautner (ARM Ltd.)

Invited Talk: Key Technologies for the Next Generation Wireless Communications (Page 266)
K.-H. Kim (Samsung Electronics)

Session A16: Synthesis Techniques for Accelerators 

Steamroller: Automatic Synthesis of Prescribed Throughput Accelerator Pipelines (Page 270)
M. Kudlur, K. Fan, S. Mahlke (University of Michigan)

Increasing Hardware Efficiency with Multifunction Loop Accelerators (Page 276)
K. Fan, M. Kudlur, H. Park, S. Mahlke (University of Michigan)

Generic Netlist Representation for System and PE Level Design Exploration (Page 282)
B. Gorjiara, M. Reshadi, P. Chandraiah, D. Gajski (University of California at Irvine)

Session A17: Communication Synthesis and Analysis for MPSoC 

Integrated Analysis of Communicating Tasks in MPSoCs (Page 288)
S. Schliecker, M. Ivers, R. Ernst (Technical University of Braunschweig)

Data Reuse Driven Energy-Aware MPSoC Co-Synthesis of Memory and Communication Architecture for Streaming Applications (Page 294)
I. Issenin, N. Dutt (University of California at Irvine)

System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis (Page 300)
S. Pasricha, Y.-H. Park, F. J. Kurdahi, N. Dutt (University of California at Irvine)