EMSOFT 2006 Table of Contents

Message from the Chairs
Sang Lyul Min & Wang Yi (Program Co-Chairs)

EMSOFT 2006 Conference Organization & Additional Reviewers

Keynote Talk

Embedded System Development for Automotive Applications: Trends and Challenges (Page 1)
W. Damm (OFFIS)

Session 1: Design and Implementation of Embedded Software 

Time-triggered Implementations of Dynamic Controllers (Page 2)
T. Nghiem (University of Pennsylvania)
G. J. Pappas (University of Pennsylvania)
A. Girard (VERIMAG)
R. Alur (University of Pennsylvania)

Efficient Distributed Deadlock Avoidance with Liveness Guarantees (Page 12)
C. Sánchez (Stanford University)
H. B. Sipma (Stanford University)
Z. Manna (Stanford University)
C. D. Gill (Washington University)

A Memory-Optimal Buffering Protocol for Preservation of Synchronous Semantics under Preemptive Scheduling (Page 21)
C. Sofronis (Verimag Laboratory)
S. Tripakis (CNRS/Verimag and Cadence Design Systems)
P. Caspi (CNRS/Verimag)

Session 2: Component-Based Development and Software Engineering

Real-Time Interfaces for Composing Real-Time Systems (Page 34)
L. Thiele, E. Wandeler, N. Stoimenov (ETH Zurich)

A Causality Interface for Deadlock Analysis in Dataflow (Page 44)
Y. Zhou , E. A. Lee (University of California at Berkeley)

Towards A Formal Foundation For Domain Specific Modeling Languages (Page 53)
E. K. Jackson, J. Sztipanovits (Vanderbilt University)

Defining a Strategy to Introduce a Software Product Line Using Existing Embedded Systems (Page 63)
K. Yoshimura (Hitachi Europe)
D. Ganesan (Fraunhofer Institute for Experimental Software Engineering)
D. Muthig (Fraunhofer Institute for Experimental Software Engineering)

Session 3: Modeling of Synchronous Systems 

Mixing Signals and Modes in Synchronous Data-flow Systems (Page 73)
J.-L. Colaço (Esterel-Technologies)
G. Hamon (The MathWorks)
M. Pouzet (Université Paris-Sud 11)

Polychronous Mode Automata (Page 83)
J.-P. Talpin (IRISA/INRIA-Rennes)
C. Brunette (IRISA/INRIA-Rennes)
T. Gautier (IRISA/INRIA-Rennes)
A. Gamatié (INRIA Futurs)

A Timing Model for Synchronous Language Impementations in Simulink (Page 93)
T. Bourke (University of NSW)
A. Sowmya (UNSW/National ICT Australia)

Session 4: Networked Embedded Software 

S2DB: A Novel Simulation-Based Debugger for Sensor Network Applications (Page 102)
Y. Wen, R. Wolski, S. Gurun (University of California at Santa Barbara)

Multi-level Software Reconfiguration for Sensor Networks (Page 112)
R. Balani, C.-C. Han, R. K. Rengaswamy, I. Tsigkogiannis, M. Srivastava (University of California at Los Angeles)

An Analysis Framework for Network-Code Programs (Page 122)
M. Anand, S. Fischmeister, I. Lee (University of Pennsylvania)

Session 5: Concurrent Real-Time Programming 

A Hierarchical Coordination Language for Interacting Real-Time Tasks (Page 132)
A. Ghosal (University of California at Berkeley)
T. A. Henzinger (EPFL)
D. Iercan (Politehnica University of Timisoara)
C. M. Kirsch (University of Salzburg)
A. Sangiovanni-Vincentelli (University of California at Berkeley)

Scheduling-Independent Threads and Exceptions in SHIM (Page 142)
O. Tardieu, S. A. Edwards (Columbia University)

Communication by Sampling in Time-Sensitive Distributed Systems (Page 152)
A. Benveniste (INRIA/IRISA)
B. Caillaud (INRIA/IRISA)
L. P. Carloni (Columbia University)
P. Caspi (CNRS/Verimag)
A. L. Sangiovanni-Vincentelli (University of California at Berkeley)
S. Tripakis (CNRS/Verimag and Cadence Berkeley Labs.)

Session 6: Software Support for Portable Storage

A Superblock-based Flash Translation Layer for NAND Flash Memory (Page 161)
J.-U. Kang, H. Jo, J.-S. Kim, J. Lee (Korea Advanced Institute of Science and Technology)

Energy-Efficient File Placement Techniques for Heterogeneous Mobile Storage Systems (Page 171)
Y.-J. Kim, K.-T. Kwon, J. Kim (Seoul National University)

Reliability Mechanisms for File Systems Using Non-Volatile Memory as a Metadata Store (Page 178)
K. M. Greenan, E. L. Miller (University of California at Santa Cruz)

Session 7: Compiling and Program Transformations 

Efficient Exception Handling in Java Bytecode-to-C Ahead-of-Time Compiler for Embedded Systems (Page 188)
D.-H. Jung, JK. Park, S.-H. Bae, J. Lee, S.-M. Moon (Seoul National University)

Schedulable Persistence System for Real-Time Applications in Virtual Machine (Page 195)
O. Goh (Arizona State University)
Y.-H. Lee (Arizona State University)
Z. Kaakani (Honeywell International Inc.)
E. Rachlin (Honeywell International Inc.)

Implementing Fault-Tolerance in Real-Time Systems by Automatic Program Transformations (Page 205)
T. Ayav, P. Fradet, A. Girault (INRIA Rhône-Alpes)

Session 8: Energy Adaptation and Optimization

Energy-Efficient Dynamic Memory Allocators at the Middleware Level of Embedded Systems (Page 215)
S. Mamagkakis (VLSI Center-Democritus University & IMEC vzw)
D. Atienza (DACYA/UCM)
C. Poucet (IMEC vzw)
F. Catthoor (IMEC vzw)
D. Soudris (VLSI Center-Democritus University)

Energy Adaptation for Multimedia Information Kiosks (Page 223)
R. Urunuela (EMN-INRIA)
G. Muller (EMN-INRIA)
J. L. Lawall (University of Copenhagen)

Compiler-Assisted Leakage Energy Optimization for Clustered VLIW Architectures (Page 233)
R. Nagpal, Y. N. Srikant (Indian Institute of Science)

Session 9: Modeling and Validation 

Analysis of the Zeoconf Protocol Using UPPAAL (Page 242)
B. Gebremichael (Radboud University)
F. Vaandrager (Radboud University)
M. Zhang (Tongji University)

Reusable Models for Timing and Liveness Analysis of Middleware for Distributed Real-Time and Embedded Systems (Page 252)
V. Subramonian (Washington University)
C. Gill (Washington University)
C. Sánchez (Stanford University)
H. B. Sipma (Stanford University)

Software Partitioning for Effective Automated Unit Testing (Page 262)
A. Chakrabarti (University of California at Berkeley)
P. Godefroid (Bell Laboratories)

Session 10: Scheduling and Execution Time Analysis 

Incremental Schedulability Analysis of Hierarchical Real-Time Components (Page 272)
A. Easwaran, I. Shin, O. Sokolsky, I. Lee (University of Pennsylvania)

Scheduling for Multi-Threaded Real-Time Programs via Path Planning (Page 282)
T. Dang (CNRS/VERIMAG)
P. Gerner (MODULOPI)

Modeling a System Controller for Timing Analysis (Page 292)
S. Thesing (Saarland University)

Session 11: Architectures and Performance Analysis 

New Approach to Architectural Synthesis: Incorporating QoS Constraint (Page 301)
H. Dhand (Philips Research)
B. Dwivedi (Calypto Design Systems)
M. Balakrishnan (IIT Delhi)

Formal Performance Evaluation of AMBA-based System-on-Chip Designs (Page 311)
G. Madl (University of California at Irvine)
S. Pasricha (University of California at Irvine)
Q. Zhu (Fujitsu Laboratories Ltd.)
L. A. D. Bathen (University of California at Irvine)
N. Dutt (University of California at Irvine)

Scratchpad Memory Management for Portable Systems with a Memory Management Unit (Page 321)
B. Egger, J. Lee, H. Shin (Seoul National University)