CASES'07 Table of Contents

Message from the CASES 2007 Conference Chairs

Organization List

Additional Reviewers

Tutorial

Compiling Code Accelerators for FPGAs (Page 1)
Walid A. Najjar (University of California Riverside)

Session 1: Embedded Development Tools

A Fast and Generic Hybrid Simulation Approach Using C Virtual Machine (Page 3)
Lei Gao (RWTH Aachen University)
Stefan Kraemer (RWTH Aachen University)
Rainer Leupers (RWTH Aachen University)
Gerd Ascheid (RWTH Aachen University)
Heinrich Meyr (RWTH Aachen University)

Compiler Generation from Structural Architecture Descriptions (Page 13)
Florian Brandner (Technischen Universität Wien)
Dietmar Ebner (Technischen Universität Wien)
Andreas Krall (Technischen Universität Wien)

Non-Transparent Debugging for Software-Pipelined Loops (Page 23)
Hugo Venturini (Verimag / STMicroelectronics)
Frédéric Riss (STMicroelectronics)
Jean-Claude Fernandez (Verimag)
Miguel Santana (STMicroelectronics)

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Session 2: Short Presentations with Posters

An Integrated ARM and Multi-core DSP Simulator (Page 33)
Sharad Singhai (Sandbridge Technologies Inc.)
Ming-Yung Ko (Sandbridge Technologies Inc.)
Sanjay Jinturkar (Sandbridge Technologies Inc.)
Mayan Moudgill (Sandbridge Technologies Inc.)
John Glossner (Sandbridge Technologies Inc.)

SCCP/x - A Compilation Profile to Support Testing and Verification of Optimized Code (Page 38)
Raimund Kirner (Technische Universität Wien)

Performance-Driven Syntax-Directed Synthesis of Asynchronous Processors (Page 43)
Luis A. Plana (The University of Manchester)
Doug Edwards (The University of Manchester)
Sam Taylor (The University of Manchester)
Luis A. Tarazona (The University of Manchester)
Andrew Bardsley (The University of Manchester)

Stack Size Reduction of Recursive Programs (Page 48)
Stefan Schaeckeler (Santa Clara University)
Weijia Shang (Santa Clara University)

Performance Evaluation and Optimization of Dual-Port SDRAM Architecture for Mobile Embedded Systems (Page 53)
Hoeseok Yang (Seoul National University)
Sungchan Kim (Seoul National University)
Hae-woo Park (Seoul National University)
Jinwoo Kim (Seoul National University)
Soonhoi Ha (Seoul National University)

A Hybrid Code Compression Technique using Bitmask and Prefix Encoding with Enhanced Dictionary Selection (Page 58)
Syed Imtiaz Haider (Virginia Polytechnic Institute and State University)
Leyla Nazhandali (Virginia Polytechnic Institute and State University)

Session 3: Scratchpad Memories

Invited Talk: Techniques for Code and Data Management in the Local Stores of the Cell Processor (Page 63)
Kevin O'Brien (IBM T.J. Watson Research Center)

Recursive Function Data Allocation to Scratch-Pad Memory (Page 65)
Angel Dominguez (University of Maryland)
Nghi Nguyen (University of Maryland)
Rajeev Barua (University of Maryland)

Fragment Cache Management for Dynamic Binary Translators in Embedded Systems with Scratchpad (Page 75)
José Baiocchi (University of Pittsburgh)
Bruce R. Childers (University of Pittsburgh)
Jack W. Davidson (University of Virginia)
Jason D. Hiser (University of Virginia)
Jonathan Misurda (University of Pittsburgh)

Scratch-Pad Memory Allocation without Compiler Support for Java Applications (Page 85)
Nghi Nguyen (University of Maryland)
Angel Dominguez (University of Maryland)
Rajeev Barua (University of Maryland)

Session 4A: Applications

Towards Understanding Architectural Tradeoffs in MEMS Closed-Loop Feedback Control (Page 95)
Greg Hoover (University of California, Santa Barbara)
Forrest Brewer (University of California, Santa Barbara)
Timothy Sherwood (University of California, Santa Barbara)

Application Driven Embedded System Design: A Face Recognition Case Study (Page 103)
Karthik Ramani (University of Utah)
Al Davis (University of Utah)

Hierarchical Coarse-grained Stream Compilation for Software Defined Radio (Page 115)
Yuan Lin (University of Michigan at Ann Arbor)
Manjunath Kudlur (University of Michigan at Ann Arbor)
Scott Mahlke (University of Michigan at Ann Arbor)
Trevor Mudge (University of Michigan at Ann Arbor)

Session 4B: Instruction-Set Extension

Rethinking Custom ISE Identification: A New Processor-Agnostic Method (Page 125)
Ajay K. Verma (Ecole Poletechnique Federale de Lausanne)
Philip Brisk (Ecole Poletechnique Federale de Lausanne)
Paolo Ienne (Ecole Poletechnique Federale de Lausanne)

An Efficient Framework for Dynamic Reconfiguration of Instruction-Set Customization (Page 135)
Huynh Phung Huynh (National University of Singapore)
Joon Edward Sim (National University of Singapore)
Tulika Mitra (National University of Singapore)

Session 5: Short Presentations with Posters

Lightweight Barrier-Based Parallelization Support for Non-Cache-Coherent MPSoC Platforms (Page 145)
Andrea Marongiu (University of Bologna)
Luca Benini (University of Bologna)
Mahmut Kandemir (Pennsylvania State University)

Light-weight Synchronization for Inter-processor Communication Acceleration on Embedded MPSoCs (Page 150)
Chengmo Yang (University of California at San Diego)
Alex Orailoglu (University of California at San Diego)

Supporting Multithreading in Configurable Soft Processor Cores (Page 155)
Roger Moussali (American University of Beirut)
Nabil Ghanem (American University of Beirut)
Mazen A. R. Saghir (American University of Beirut)

A Group-Based Wear-Leveling Algorithm for Large-Capacity Flash Memory Storage Systems (Page 160)
Dawoon Jung (Korea Advanced Institute of Science and Technology)
Yoon-Hee Chae (Korea Advanced Institute of Science and Technology)
Heeseung Jo (Korea Advanced Institute of Science and Technology)
Jin-Soo Kim (Korea Advanced Institute of Science and Technology)
Joonwon Lee (Korea Advanced Institute of Science and Technology)

Facilitating Compiler Optimizations through the Dynamic Mapping of Alternate Register Structures (Page 165)
Chris Zimmer (Florida State University)
Stephen Hines (Florida State University)
Prasad Kulkarni (Florida State University)
Gary Tyson (Florida State University)
David Whalley (Florida State University)

Session 6: Memory Systems

Vertical Object Layout and Compression for Fixed Heaps (Page 170)
Ben L. Titzer (University of California, Los Angeles)
Jens Palsberg (University of California, Los Angeles)

Software Controlled Memory Layout Reorganization for Irregular Array Access Patterns (Page 179)
Doosan Cho (Seoul National University)
Ilya Issenin (University of California, Irvine)
Nikil Dutt (University of California, Irvine)
Jonghee W. Yoon (Seoul National University)
Yunheung Paek (Seoul National University)

A Self-Maintained Memory Module Supporting DMM (Page 189)
Weixing JI (Beijing Institute of Technology)
Feng Shi (Beijing Institute of Technology)
Baojun Qiao (Beijing Institute of Technology)

Eliminating Inter-Process Cache Interference through Cache Reconfigurability for Real-Time and Low-Power Embedded Multi-Tasking Systems (Page 198)
Rakesh Reddy (University of Maryland)
Peter Petrov (University of Maryland)

Keynote

Multicore Architectures (Page 208)
Trevor Mudge (The University of Michigan)

Session 7: Compilation/Code Generation

An Optimistic and Conservative Register Assignment Heuristic for Chordal Graphs (Page 209)
Philip Brisk (Ecole Polytechnique Federale de Lausanne)
Ajay K. Verma (Ecole Polytechnique Federale de Lausanne)
Paolo Ienne (Ecole Polytechnique Federale de Lausanne)

A Simplified Java Bytecode Compilation System for Resource-Constrained Embedded Processors (Page 218)
Carmen Badea (University of California, Irvine)
Alexandru Nicolau (University of California, Irvine)
Alexander V. Veidenbaum (University of California, Irvine)

A Backtracking Instruction Scheduler using Predicate-based Code Hoisting to Fill Delay Slots (Page 229)
Tom Vander Aa (IMEC)
Bing-Feng Mei (IMEC)
Bjorn De Sutter (IMEC)

Session 8: Low Power and Thermal-Aware Architectures

INTACTE: An Interconnect Area, Delay, and Energy Estimation Tool for Microarchitectural Explorations (Page 238)
Rahul Nagpal (Indian Institute of Science)
Arvind Madan (Indian Institute of Science)
Amrutur Bhardwaj (Indian Institute of Science)
Y. N. Srikant (Indian Institute of Science)

Cache Leakage Control Mechanism for Hard Real-Time Systems (Page 248)
Jaw-Wei Chi (National Taiwan University)
Chia-Lin Yang (National Taiwan University)
Yi-Jung Chen (National Taiwan University)
Jien-Jia Chen (National Taiwan University)

Performance Optimal Processor Throttling Under Thermal Constraints (Page 257)
Ravishankar Rao (Arizona State University)
Sarma Vrudhula (Arizona State University)

A Low Power Front-End for Embedded Processors Using a Block-Aware Instruction Set (Page 267)
Ahmad Zmily (Stanford University)
Christos Kozyrakis (Stanford University)