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CODES+ISSS'07 Table of Contents CODES+ISSS 2007 Organizing Committee Sunday, September 30th Tutorials Beyond
Gaming: Programming the PLAYSTATION3 Cell Architecture for Cost-Effective Compiling Code Accelerators for FPGAs (Page 2) |
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Monday, October 1st Session 1A: System-Level Design Methods for MPSoC Simultaneous Synthesis of Buses, Data Mapping and Memory Allocation for MPSoC (Page 3) A Framework for Rapid System-level Exploration, Synthesis, and Programming Predictable Execution Adaptivity through Embedding Dynamic Reconfigurability |
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Session 1B: Specification Language and Model Synchronization after Design Refinements with Sensitive Delay Elements (Page 21) Embedded Software Development on Top of Transaction-Level Models (Page 27) Pointer Re-coding for Creating Definitive MPSoC Models (Page 33) |
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Session 2A: Embedded Systems Dynamic Security Domain Scaling on Symmetric Multiprocessors for Future Secure FPGA Circuits Using Controlled Placement and Routing (Page 45) A Smart Random Code Injection to Mask Power Analysis Based Side Channel Attacks (Page 51) Ensuring Secure Program Execution in Multiprocessor Embedded Systems: A Case Study (Page 57) |
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Session 2B: Heterogeneous Computing Platform Simulation and Debug Combined Approach to System Level Performance Analysis of Embedded Systems (Page 63) Event-based Re-training of Statistical Contention Models for Heterogeneous Multiprocessors (Page 69) HySim: A Fast Simulation Framework for Embedded Software Development (Page 75) A Computational Reflection Mechanism to Support Platform Debugging in SystemC (Page 81) |
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Session 3A: Static and Dynamic Techniques for Partitioning and Scheduling Energy Efficient Co-scheduling in Dynamically Reconfigurable Systems (Page 87) Thread Warping: A Framework for Dynamic Synthesis of Thread Accelerators (Page 93) HW/SW Co-Design for Esterel Processing (Page 99) Session 3B: Low Power Design and Thermal Control Power Deregulation: Eliminating Off-Chip Voltage Regulation Circuitry From Embedded Systems (Page 105) Temperature-Aware Processor Frequency Assignment for MPSoCs Using Convex Optimization (Page 111) Three-Dimensional Multiprocessor System-on-Chip Thermal Optimization (Page 117) |
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Tuesday, October 2nd Keynote Complexity Challenges Towards 4th Generation Communication Solutions (Page 123) Special Session I Fresh Air: The Emerging Landscape of Design for Networked Embedded Systems (Page 124) |
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Session 4A: Embedded Software Locality Optimization in Wireless Applications (Page 125) A Code-Generator Generator for Multi-Output Instructions (Page 131) Influence of Procedure Cloning on WCET Prediction (Page 137) Compile-Time Decided Instruction Cache Locking Using Worst-Case Execution Paths (Page 143) Session 4B: Advances in NoC Optimization Channel Trees: Reducing Latency by Sharing Time Slots in Time-Multiplexed Networks on Chip (Page 149) Performance and Resource Optimization of NoC Router Architecture for Master and Slave IP Cores (Page 155) Incremental Run-time Application Mapping for Homogeneous NoCs with Multiple Voltage Levels (Page 161) A Data Protection Unit for NoC-based Architectures (Page 167) |
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Session 5A: System-Level Performance Analysis Complex Task Activation Schemes in System Level Performance Analysis (Page 173) Improved Response Time Analysis of Tasks Scheduled under Preemptive Round-Robin (Page 179) Probabilistic Performance Risk Analysis at System-Level (Page 185) Session 5B: Case Studies and Emerging Techniques ESL Design and HW/SW Co-verification of High-end Software Defined Radio Platforms (Page 191) Smart Driver for Power Reduction in Next Generation Bistable Electrophoretic Display Technology (Page 197) On the Impact of Manufacturing Process Variations on the Lifetime of Sensor Networks (Page 203) |
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Wednesday, October 3rd Special Session II: Practical Approaches to System-level Performance Analysis Performance Modeling for Early Analysis of Multi-Core Systems (Page 209) Bridging Gap between Simulation and Spreadsheet Study (Page 215) Performance Analysis and Design Space Exploration for High-End Biomedical Applications: Challenges and Solutions (Page 217) |
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Session 6A: System-Level Synthesis A Low Power VLIW Processor Generation Method by Means of Extracting Non-redundant Activation Conditions (Page 227) Scheduling and Voltage Scaling for Energy/Reliability Trade-offs in Fault-Tolerant Time-Triggered Embedded Systems (Page 233) Reliable Multiprocessor System-On-Chip Synthesis (Page 239) Session 6B: Embedded Systems Architecture Aggressive Snoop Reduction for Synchronized Producer-Consumer Communication in Energy-Efficient Embedded Multi-Processors (Page 245) Predator: A Predictable SDRAM Memory Controller (Page 251) Performance Improvement of Block Based NAND Flash Translation Layer (Page 257) |
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Panel Automotive Networks—Are New Busses and Gateways the Answer or Just Another Challenge? (Page 263) |
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