Welcome

Table of Contents

Author Index

EMSOFT 2005 Organization

Program Committee

Additional Reviewers

Sponsor & Supporters

Session 1: Communication and Devices               (Return to Contents)

HAIL: A Language for Easy and Correct Device Access (Page 1)
J. Sun, W. Yuan, M. Kallahalla, N. Islam (DoCoMo Communication Laboratories USA, Inc.)

A Structural Approach to Quasi-Static Schedulability Analysis of Communicating Concurrent Programs (Page 10)
C. Liu (University of California at Berkeley)
A. Kondratyev, Y. Watanabe (Cadence Berkeley Labs)
A. Sangiovanni-Vincentelli (University of California at Berkeley)

Centralized End-to-End Flow Control in a Best-Effort Network-on-Chip (Page 17)
P. Avasare, V. Nollet, J.-Y. Mignolet (IMEC V.Z.W.)
D. Verkest (IMEC V.Z.W., Vrije Universiteit Brussel and Katholieke Universiteit Leuven)
H. Corporaal (Technical University Eindhoven)

Communication Strategies for Shared-Bus Embedded Multiprocessors (Page 21)
N. K. Bambha (US Army Research Lab.)
S. S. Bhattacharyya (University of Maryland, College Park)

Session 2: Modeling               (Return to Contents)

Using Separation of Concerns for Embedded Systems Design (Page 25)
E. K. Jackson, J. Sztipanovits (Vanderbilt University)

Toward a Semantic Anchoring Infrastructure for Domain-Specific Modeling Languages (Page 35)
K. Chen, J. Sztipanovits, S. Neema (Vanderbilt University)

Uniform Object Modeling Methodology and Reuse of Real-time System Using UML (Page 44)
B. M. Duc (Laval University)

From Statecharts to ESP*: Programming With Events, States and Predicates For Embedded Systems (Page 48)
V. C. Sreedhar, M.-C. Marinescu (IBM T.J. Watson Research Center)

Session 3: Languages               (Return to Contents)

High Performance Annotation-aware JVM for Java Cards (Page 52)
A. Azevedo, A. Kejariwal, A. Veidenbaum, A. Nicolau (University of California at Irvine)

Deeply Embedded XML Communication – Towards an Interoperable and Seamless World (Page 62)
J. Helander (Microsoft Research)

High-level Real-time Programming in Java (Page 68)
D. F. Bacon, P. Cheng, D. Grove, M. Hind, V. T. Rajan, E. Yahav (IBM T.J. Watson Research Center)
M. Hauswirth (Università della Svizzera)
C. M. Kirsch (Universität Salzburg)
D. Spoonhower (Carnegie Mellon University)
M. T. Vechev (University of Cambridge)

Panel 1               (Return to Contents)

What will System Level Design be When It Grows Up? (Page 79)
G. Martin (Tensilica)
D. Gajski (University of California at Irvine)
D. Goodwin (Tensilica)
P. Lysaght (Xilinx Research)
P. Marwedel (University of Dortmund)
M. Muller (ARM, UK)
J. Welser (IBM)

Session 4: Scheduling               (Return to Contents)

Real-Time Interfaces for Interface-Based Design of Real-Time Systems with Fixed Priority Scheduling (Page 80)
E. Wandeler, L. Thiele (Swiss Federal Institute of Technology (ETH))

QoS Control for Optimality and Safety (Page 90)
J. Combaz (Verimag/STMicroelectronics)
J.-C. Fernandez (Verimag)
T. Lepley (STMicroelectronics)
J. Sifakis (Verimag)

Model-Based Run-Time Monitoring of End-to-End Deadlines (Page 100)
J. Ahluwalia, I. H. Krüger, W. Phillips (University of California at San Diego)
M. Meisinger (Technische Universität München)

A GA-Based Scheduling Method for FlexRay Systems (Page 110)
S. Ding, N. Murakami, H. Tomiyama, H. Takada (Nagoya University)

Session 5: Optimization               (Return to Contents)

Using De-optimization to Re-optimize Code (Page 114)
S. Hines, P. Kulkarni, D. Whalley (Florida State University)
J. Davidson (University of Virginia)

A Sink-N-Hoist Framework for Leakage Power Reduction (Page 124)
Y.-P. You, C.-W. Huang, J. K. Lee (National Tsing Hua University)

Exploiting Last Idle Periods of Links for Network Power Management (Page 134)
F. Li, G. Chen, M. Kandemir (Pennsylvania State University)
M. Karakoy (Imperial College)

A UML 2.0 Profile for SystemC: Toward High-level SoC Design (Page 138)
E. Riccobene (Univ. di Milano)
P. Scandurra (Univ. di Catania)
A. Rosti, S. Bocchio (STMicroelectronics Lab R&I)

Session 6: Design Methodologies               (Return to Contents)

Towards Real-Time Enabled Microsoft Windows (Page 142)
X. Feng (Microsoft Corporation)

Systems Architecture: The Empirical Way — Abstract Architectures to 'Optimal' Systems: Democritus and Plato Re-engage Digitally 2,400 years on! (Page 147)
G. R. Hellestrand (VaST Systems Technology Corporation)

A Unified HW/SW Interface Model to Remove Discontinuities between HW and SW Design (Page 159)
A. Bouchhima, X. Chen, F. Pétrot, W. O. Cesário, A. A. Jerraya (TIMA Laboratory)

Session 7: Specification and Semantics               (Return to Contents)

A Denotational Semantics for Stateflow (Page 164)
G. Hamon (Chalmers Institute of Technology)

A Conservative Extension of Synchronous Data-flow with State Machines (Page 173)
J.-L. Colaço, B. Pagano (Esterel-Technologies)
M. Pouzet (LRI, Université Paris-Sud)

Rialto: a Bridge between Description and Implementation of Control Algorithms for Wireless Sensor Networks (Page 183)
A. Bonivento (University of California at Berkeley)
L. P. Carloni (Columbia University)
A. L. Sangiovanni-Vincentelli (University of California at Berkeley)

Efficient Embedded Software Design with Synchronous Models (Page 187)
M. Baleani, A. Ferrari, L. Mangeruca (PARADES E.E.I.G.)
A. Sangiovanni-Vincentelli (PARADES E.E.I.G., University of California at Berkeley)

Session 8: Compilation and Power               (Return to Contents)

Code Aware Resource Management (Page 191)
L. de Alfaro, V. Raman (University of California at Santa Cruz)
M. Faella (University of California at Santa Cruz, Università di Napoli)
R. Majumdar (University of Calfornia at Los Angeles)

Compiler-guided Register Reliability Improvement Against Soft Errors (Page 203)
J. Yan, W. Zhang (Southern Illinois University Carbondale)

Distributed-Code Generation from Hybrid Systems Models for Time-delayed Multirate Systems (Page 210)
M. Anand, S. Fischmeister, J. Kim, I. Lee (University of Pennsylvania)

Power Consumption Profile Analysis for Security Attack Simulation in Smart Cards at High Abstraction Level (Page 214)
K. Rothbart, U. Neffe, Ch. Steger, R. Weiss (Graz University of Technology)
E. Rieger, A. Muehlberger (Philips Austria GmbH Styria)

Session 9: Clocks and Energy               (Return to Contents)

AutoDVS: An Automatic, General-Purpose, Dynamic Clock Scheduling System for Hand-Held Devices (Page 218)
S. Gurun, C. Krintz (University of California at Santa Barbara)

Optimizing Inter-Processor Data Locality on Embedded Chip Multiprocessors (Page 227)
G. Chen, M. Kandemir (The Pennsylvania State University)

A Formal Approach to Fault Tree Synthesis for the Analysis of Distributed Fault Tolerant Systems (Page 237)
M. L. McKelvin, Jr., G. Eirea (University of Calfornia at Berkeley)
C. Pinello, S. Kanajan (General Motors Berkeley Lab)
A. L. Sangiovanni-Vincentelli (University of Calfornia at Berkeley)

(1+?) Approximation Clock Rate Assignment for Periodic Real-Time Tasks on A Voltage-Scaling Processor (Page 247)
J.-J. Chen, T.-W. Kuo, C.-S. Shih (National Taiwan University)

Minimizing Expected Energy in Real-Time Embedded Systems (Page 251)
R. Xu, D. Mossé, R. Melhem (University of Pittsburgh)

Session 10: Formal Methods               (Return to Contents)

Tag Machines (Page 255)
A. Benveniste, B. Caillaud, (IRISA/INRIA)
L. P. Carloni (Columbia University)
A. L. Sangiovanni-Vincentelli (University of California at Berkeley)

SHIM: A Deterministic Model for Heterogeneous Embedded Systems (Page 264)
S. A. Edwards, O. Tardieu (Columbia University)

Semantics-Based Optimization Across Uncoordinated Tasks in Networked Embedded Systems (Page 273)
J. Liu (Microsoft Research)
E. Cheong (University of California at Berkeley)
F. Zhao (Microsoft Research)

From Multi-clocked Synchronous Processes to Latency-insensitive Modules (Page 282)
J.-P. Talpin, D. Potop-Butucaru, J. Ouy, B. Caillaud (INRIA - IRISA)

The Formal Verification of a Reintegration Protocol (Page 286)
L. Pike (NASA Langley Research Center)
S. D. Johnson (Indiana University)

Session 11: Software Testing               (Return to Contents)
Session Chair: I. Harris (University of California at Irvine)

Random Testing of Interrupt-Driven Software (Page 290)
J. Regehr (University of Utah)

Testing Real-Time Embedded Software using UPPAAL-TRON: An Industrial Case Study (Page 299)
K. G. Larsen, M. Mikucionis, B. Nielsen, A. Skou (Aalborg University)

Cutpoints for Formal Equivalence Verification of Embedded Software (Page 307)
X. Feng, A. J. Hu (University of British Columbia)

Session 12: Specification and Dynamic Properties               (Return to Contents)

PINAPA: An Extraction Tool for SystemC Descriptions of Systems-on-a-Chip (Page 317)
M. Moy (Verimag, STMicroelectronics)
F. Maraninchi (Verimag)
L. Maillet-Contoz (STMicroelectronics)

Distributing Synchronous Programs Using Bounded Queues (Page 325)
M. Zennaro, R. Sengupta (University of California at Berkeley)

Dynamic Online Reconfiguration for Customizable and Self-Optimizing Operating Systems (Page 335)
S. Oberthür, C. Böke, B. Griese (University of Paderborn)

Synchronization of Periodic Clocks (Page 339)
A. Cohen (Paris-Sud University)
M. Duranton (Philips Research Laboratories)
C. Eisenbeis, C. Pagetti, F. Plateau, M. Pouzet (Paris-Sud University)

Session 13: Real Time Properties               (Return to Contents)

Passive Mid-Stream Monitoring of Real-Time Properties (Page 343)
L. J. Jagadeesan, R. Viswanathan (Bell Laboratories Research, Lucent Technologies)

Semantics-Preserving and Memory-Efficient Implementation of Inter-Task Communication on Static-Priority or EDF Schedulers (Page 353)
S. Tripakis, C. Sofronis, N. Scaife, P. Caspi (Verimag Laboratory)

Dual Face Phased Array Radar Scheduling with Multiple Constraints (Page 361)
Q. Cao, J. A. Stankovic (University of Virginia)

Model-based Analysis of Distributed Real-time Embedded System Composition (Page 371)
G. Madl (University of California at Irvine)
S. Abdelwahed (Vanderbilt University)

Panel 2               (Return to Contents)

Grand Challenges in Embedded Systems (Page 375)
J. Sztipanovits (Vanderbilt University)
J. Glossner (Sandbridge Technologies)
C. Rowen (Tensilica)
W. Wolf (Princeton University)
T. Mudge (University of Michigan, Ann Arbor)
A. Sangiovanni-Vincentelli (University of California at Berkeley)
F. Zhao (Microsoft Research)